Group III-V elements may be advantageous in certain applications for silicon-based devices, for example, source/drain materials or the like, due to low contact resistance and the ability to function as a stressor for mobility enhancement in silicon-based devices. However, defects during heteroepitaxy of Group III-V elements on silicon arise from material incompatibilities such as large lattice mismatch (>4%), valence difference, thermal property differences, and conductivity differences. The defects may include dislocations, anti-phase boundaries, and stacking faults for Group III-V layers. Group III-V features are frequently formed in trenches. However, with smaller device size requirements, Group III-V element growth inside high aspect ratio (depth vs. opening width) trenches becomes increasingly difficult.
Group III-V element channels are generally formed in an array of nanometer scale planar or vertical structures with critical dimensions of about 5-15 nm and depths of about 20-100 nm. Requirements for high quality Group III-V element channels are desired, such as having minimal defects (<10−5/cm2), consistent and controlled composition and morphology, and no parallel conduction of carriers other than in the active device region of the channel structures. Forming high quality Group III-V element channels is challenging given the desire for increasingly small device sizes and the aforementioned minimization of defects present in the devices.
Thus, there is a need for high quality Group III-V element channels with small device sizes.